1. Field of the Present Invention
The present invention generally relates to the field of microprocessors and more particularly to a microprocessor utilizing a secondary reorder buffer for instructions with multiple targets.
2. History of Related Art
The use of reorder buffers in microprocessors to enable out-of-order execution is well known. See, e.g., Hennessy and Patterson, Computer Architecture a Quantitative Approach, pp. 309-317 (Morgan Kaufmann 2d ed. 1996). Reorder buffers are used to store results of executed instructions until an instruction is finally committed. Many superscalar processors allow multiple instructions to issue in a single cycle. To achieve maximum performance, rename register allocation for each issued instruction should occur in the cycle in which the instruction is issued. Typically, each issued instruction affects the contents of a single register in the microprocessor and therefore requires just a single rename register entry. In other cases, however, an instruction (referred to herein as a complex instruction) affects the contents of two or more registers. Register renaming for these complex instructions should also occur in the issue cycle if optimum performance is to be achieved. Unfortunately, the renaming buffers employed in conventional microprocessors are limited in the number of allocations they can perform in a single cycle. This limitation on the number of rename allocations that can occur in a single cycle coupled with the existence of instructions requiring multiple allocations complicates the issue unit and can result in the issue unit being unable to issue the maximum number of instructions in a particular cycle if one of the instructions is a complex instruction. Therefore it would be desirable to implement a microprocessor capable of issuing the maximum number of instructions per cycle regardless of whether the instructions include simple instructions, complex instructions, or a combination of both.
The problem identified above is in large part addressed by a method, processor, and data processing system for enabling maximum instruction issue per cycle despite the presence of complex instructions that require multiple rename registers. The method includes allocating a first rename register in a first reorder buffer for storing the contents of a first register affected by the complex instruction. A second rename register in a second reorder buffer is then allocated for storing the contents of a second register affected by the complex instruction. In an embodiment in which the first reorder buffer supports a maximum number of allocations per cycle, the allocation of the second register using the second reorder buffer prevents the complex instruction from requiring multiple allocation slots in the first reorder buffer. The method may further include issuing a second instruction that contains a dependency on a register that is allocated in the secondary reorder buffer. In one embodiment, reorder buffer information indicating the second instruction""s dependence on a register allocated in the secondary reorder buffer is associated with the second instruction such that, when the second instruction is issued subsequently, the reorder buffer information is used to restrict the issue unit to checking only the secondary reorder buffer for dependencies.